By Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
This booklet constitutes the refereed court cases of the eleventh foreign Symposium on utilized Reconfigurable Computing, ARC 2015, held in Bochum, Germany, in April 2015.
The 23 complete papers and 20 brief papers awarded during this quantity have been conscientiously reviewed and chosen from eighty five submissions. they're prepared in topical headings named: structure and modeling; instruments and compilers; structures and functions; network-on-a-chip; cryptography purposes; prolonged abstracts of posters. moreover, the e-book includes invited papers on funded R&D - operating and accomplished tasks and Horizon 2020 funded projects.
Read or Download Applied Reconfigurable Computing: 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings PDF
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Extra info for Applied Reconfigurable Computing: 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings
41(6) (1997) 10. : Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buﬀers. In: Proc. of the Int. Symp. on Computer Architecture (1990) 11. : Chisel: constructing hardware in a scala embedded language. In: Proc. E. com Abstract. Dynamic power-gating has been shown to reduce FPGA static leakage power signiﬁcantly. In this paper, we propose a high-level synthesis (HLS) compiler-assisted framework that automatically detects the hierarchical power-gating opportunities, and turns oﬀ accelerators when they are not required.
In Section 5, we evaluate the impact of changing inputs on the number of idle periods and their duration. 3 Pruning Idle Periods The previous phase produces a list of all potential power-gating opportunities. However, many of these may not be proﬁtable. Powering down (and later powering up) a power-gated region incurs both energy and delay overhead. Thus, for each power-gating opportunity, we must determine whether a power-gating event should be generated. In general, an accelerator should be turned oﬀ when idle if the power saved by power-gating the accelerator is more than the overhead of turning the accelerator oﬀ and then on again at the end of the idle period.
Fortunately, algorithms that make heavy use of SpMV tend to multiply the same sparse matrix with many diﬀerent vectors, which enables ameliorating the cost of preprocesing across speed-ups in each SpMV iteration. This preprocessing can take many forms , including permuting rows/columns to create dense structure, decomposing into predetermined patterns, mapping to parallel processing elements to minimize communication and so on. We also adopt a preprocessing step in our scheme to enable optimizing for a given sparse matrix, but unlike previous work, our preprocessing stage produces information to enable specialized cache operation instead of changing the matrix structure.